Senior Engineer

PI(Frontend) Jobs: Design synthesis, layout information for place/cts/routing, cross check the QoR of place/CTS/routing,

make timing constraints(sdc),

timing eco (fix timing, fix drc – mttv, glitch noise, cpc, min_pulse), Equivalen check,Special clock net care,low power rule check,leakage optimization (w/ TECO),

PI(Frontend) tools: Design-compiler, DCG, PrimeTime, Formality, VCLP, GCA,Spyglass-LDRC

Responsibilities

• Solid experience in developing and owning full chip timing constraints for a complex, multi-voltage SoCs.
• Solid experience in running physical-aware logic synthesis (DC-G or Genus) and achieving optimal synthesis QoR on high-performance and low power designs
• Solid experience in developing power intent using UPF and running static low power verification tool like Synopsys VC-LP or similar tools
• Solid experience in running gate level power estimation using Synopsys PrimeTime-PX
• Developing the timing constraints and running the full-chip logic synthesis
• Collaborating with DSP to accomplish the design closure for tape-out
• Block-level PPA analysis for marketing and sales/BD support
• Samsung design methodology support for ASIC customers
• Good understanding of chip floor plan to get the best PPA during physical-aware synthesis