ASIC Engineers

Imagine being part of a team that is constantly disrupting the industry and changing the way people communicate, collaborate as well as explore our world through all forms of entertainment. We have created an Intelligent Transport Network with more speed, capacity and scalability than ever before, utilizing our industry disrupting technology. Imagine a world with unlimited bandwidth to provide endless possibilities. Our network of tomorrow will allow for content and creativity limited only by the limits of your imagination.

We are looking for ASIC Design and Verification Engineers off all levels from Senior to Principal, that are ready to take on new challenges and be a part of our industry disrupting teams.

Here at Infinera we value our team collaboration and autonomy. As one of our ASIC Engineers you will be responsible for macro-architecture and micro-architecture of complex ASICs and/or complex modules in ASICs. You will also be Evaluating IPs, methodologies, tools & vendors and providing recommendations for IP/Methodology/Tool/Vendor selection. You will collaborate and contribute on our new product development, as well as work closely across multiple divisions and teams at Infinera.

We would like to welcome you to our industry leading, disrupting and standard setting teams if you have….

Knowledge/Skills

• A BS in Elec/computer Engineering, Software Engineering, Information Technology or equivalent work experience (for our Staff to Principal Engineers we’d like you to have a MS or Ph, D or Equivalent work experience)
• 3 to 12+ years’ experience in ASIC Design and/or Verification
• Knowledge of System Verilog, C/C++, and scripting languages like Python or Perl Experience of code design and writing testable code
• Highly motivated industry disrupting team player
• Familiarity with assertions and functional coverage
• Excellent communication skills and the ability to work across multi-functional and geographically diverse team environments
• Develop System Verilog/UVM based environment components, for use in the verification of DSP algorithms, ARM-based Control Planes, and/or Networking Protocols.
• Responsible for the definition, development, and execution of self-checking tests.
• Cross-functional support of emulation, firmware development, post-silicon validation, and system integration activities.
• Develop System Verilog/UVM based environment components, for use in the verification of DSP algorithms, ARM-based Control Planes, and/or Networking Protocols.
• Design area/timing/power optimization via micro-architecture/RTL/Synthesis
• Layout support for quality final product and TTM
• Subsystem development in large mixed-signal ASICs
• Good knowledge in script/programming languages such as Perl, Python, TCL, C/C++ & Matlab

Nice To Have Skills

• Exposure to UVM methodology
• Responsible for architecture and micro-architecture of complex ASICs and/or complex modules in ASICs
• Good knowledge and experience in RTL/Synthesis based ASIC design methodology and tools
• Ethernet & OTN protocol experience is preferred
• Must have good communication skills
• Must have ability and desire to work as a team

Infinera is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, sex, color, religion, sexual orientation, gender identity, national origin, disability status, protected veteran status, or any other characteristic protected by law. Infinera complies with all applicable state and local laws governing nondiscrimination in employment.